1. Field of the Invention
The present invention relates to a metallization method for forming interconnects such as contact studs in an integrated circuit, and also relates to a metallization method for forming via plugs in a multi-level metal system.
2. Description of the Prior Art
Surface metallization is critical to the operation of a semiconductor device. Surface metallization refers to the formation of the contact point from the outside world to the integrated circuitry. These contact points are formed directly on the integrated circuit device. As the chip density increases and the function of the device becomes more complicated, it is well known that a multi-level metal (MLM) system is required to provide adequate interconnection routings in an integrated circuit.
Tungsten and aluminum are two metals commonly used to form a contact stud in the first level of a MLM system or a via plug in or above the second level of a MLM system. The deposition of the metal to fill the contact hole that contains a contact stud or the via opening that contains a via plug in the prior art usually results in a center-line seam 1. This is caused by the columnar morphology of the metal layer 2 as shown in FIG. 1A. Another defect is known as the keyhole 3 defect. It is caused by premature coalescence of the metal layer 4 as shown in FIG. 1B. Furthermore, referring to FIG. 1C, even without those defects mentioned above, the contact stud 5 formed by etching back usually possesses a dimple. After etching, the resultant contact studs 1a, 4b, and 5 are not ideally formed, making the contact with an upper-level metal contact 6 difficult.
The defects mentioned above will increase the probability of a faulty connection between the metal levels. Also, the defects will decrease the current carrying capability of the contact stud or the via plug.
Furthermore, as the density of the integrated circuit increases, the contact studs and via plugs become smaller in size. This results in the aspect ratio of the contact studs and via plugs becoming quite large. Thus, it will become increasingly difficult to fabricate reliable interconnections in an integrated circuit.
Therefore, a need has arisen in the industry for an improved process which will overcome the above defects.